This invention relates generally to ferroelectric memories. More particularly, the present invention relates to a method of fabricating a ferroelectric capacitor stack (bottom electrode, ferroelectric dielectric, top electrode) for use in an integrated circuit ferroelectric memory.
In general, prior art integrated circuit ferroelectric memories have two major problems. One of these problems is increased surface topology, which leads to manufacturability problems such as metal step coverage and the like. The second problem is related to "line degradation", which generally refers to the loss of functionality primarily due to damage experienced by the ferroelectric capacitor dielectric during the many processing steps required to fabricate a packaged ferroelectric memory. A main source of the damage can be traced to exposure of the ferroelectric capacitor dielectric to hydrogen. Prior art structures and methods of dealing with hydrogen exposure and the resultant damage and loss of functionality included placing barrier materials such as PZT or other barrier materials directly over the ferroelectric capacitor. While these prior art methods somewhat reduced line degradation, they can become compromised when the contact to the top electrode is formed. The top electrode contact becomes the entrance of a pathway for hydrogen to still attack the ferroelectric dielectric layer that is located laterally beneath the top electrode.
What is desired is a device structure for an integrated circuit ferroelectric memory that is both planar and insensitive to hydrogen-induced line degradation.